The present invention relates to semiconductor devices, and more specifically, to fabrication methods and resulting structures for a vertical transistor having uniform bottom spacers.
As demands to reduce the dimensions of transistor devices continue, new designs and fabrication techniques to achieve a reduced device footprint are developed. Vertical-type transistors such as vertical field effect transistors (vertical FETs) have recently been developed to achieve a reduced FET device footprint without comprising necessary FET device performance characteristics. When forming these vertical FETS, spacers need to be provided between and around vertical structures.